View MDT10P65_936769.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MDT10P65
1. General Description
This OTP-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of EPROM, and 192 bytes of static RAM.
3. Applications
The application areas of this MDT10P65 range from appliance motor control and high speed automotive to low power remote transmitters/receivers and telecommunications processors, such as Remote controller, small instruments, toy, automobile and keyboard ... etc.
2. Features
RISC CPU Fully static design 37 single word instructions 4K x 14 program memory. 192 bytes RAM for data 35 bi-directional I/O Eight level hardware stacks Watchdog timer with on-chip RC oscillator. Interrupt capability Timer0 : 8-bit timer with 8-bit prescaler Timer1 : 8-bit timer with 8-bit compare register. This timer can be used as carrier generator. Sleep mode for power saving. PB and PD with port change wake-up interrupt. PS : timer1 counter PC0 clock in low to high the counter data increase
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.1
2005/10 Ver1.6
MDT10P65
4. Pin Diagram
MDT10P65A3P/S 18 pin DIP/SOP MDT10P65SD42 pin Shrink PDIP PA6 1 42 PA7 /RES 2 41 PB7 PA0 3 40 PB6 PA1 4 39 PB5 PA2 5 38 PB4 PA3 6 37 PB3 PA4/T0CLK 7 36 PB2 PA5 8 35 PB1 PE0 9 34 PB0/IRQ PE1 10 33 VDD PE2 11 32 VSS VDD 12 31 PD7 VSS 13 30 PD6 OSC1 14 29 PD5 OSC2 15 28 PD4 PC0/T1OSCO 16 27 PC7 PC1/T1OSCI 17 26 PC6 PC2 18 25 PC5 PC3 19 24 PC4 PD0 20 23 PD3 PD1 21 22 PD2 MDT10P65A2Q
/RES PA2 PA3 PA4 VSS OSC1 OSC2 PC0/T1OSCO PC1/T1OSCI MDT10P65A1Q
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
PB4 PB3 PB2 PB1 PB0 VDD PC7 PC6 PC5
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.2
2005/10 Ver1.6
MDT10P65
MDT10P65 pin 28 PDIP/SOP
5. Pin function description
Pin name OSC1 OSC2 /RES(MCLRB) Type Buffer type I O I Description Oscillator input Oscillator out Reset input with 130K ohm pull-up Bi-directional I/O port A. Port A can be software programmed for internal 45K ohm pull-up on all pins except PA5. The pull-up resistance on PA5 is 100K ohm.
ST
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
I/O I/O I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL TTL TTL
Can be clock input to Timer0.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3
2005/10
Ver. 1.6
MDT10P65
Pin name Type Buffer type Description Bi-directional I/O port B. Port B can be software programmed for internal 25K ohm pull-up on all pins. PB0-PB7 can generate interrupt on pin state change. Can be the external interrupt pin.
PB0/IQR PB1 PB2 PB3 PB4 PB5 PB6 PB7
I/O I/O I/O I/O I/O I/O I/O I/O
ST/TTL TTL TTL TTL TTL TTL TTL TTL
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0-PD7
I/O I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST ST
Bi-directional I/O port C. Port C can be software programmed for internal 100K pull-up on all pins. Can be Timer1 oscillator output or Timer1 clock input. Can be Timer1 oscillator input.
Bi-directional port. All pins can generate interrupt on pin state change. Port D can be software programmed for internal 100K pull-up on all pins. Bi-directional port E. Port E can be software programmed for internal 100K pull-up on all pins.
PE0 PE1 PE2 Vdd Vss
I/O I/O I/O
ST ST ST Power input Ground pin
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4
2005/10
Ver. 1.6
MDT10P65
6. Memory Mapping
6.1Program memory : 0000h 0001h 0002h 0003h 0004h 0005h Program memory (Page 0) 07FFh 0800h Program memory (Page 1) 0FFFh Reset Vector 6.2Register file map : BANK 0 00h IAR 01h RTCC 02h PCL 03h STATUS 04h MSR 05h PORT A 06h PORT B 07h PORT C 08h PORT D 09h PORT E 0Ah PCH 0Bh INTS 0Ch PIFB1 0Dh PIFB2 0Eh TMR1L 0Fh 10h T1STA 11h 12h 13h 14h 15h CCP1L 16h 17h CCP1CTL 18h BANK 1 IAR TMR PCL STATUS MSR CPIO A CPIO B CPIO C CPIO D CPIO E PCH INTS PIEB1 PIEB2 PSTA PPHE
Peripheral interrupt Vector
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h
1Fh 20h General Purpose Register 7Fh General Purpose Register
9Fh A0h
FFh
Unimplemented memory location.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5
2005/10
Ver. 1.6
MDT10P65
00 01 02 03 Indirect addressing register Timer0 register Program counter low byte Status register Bit 0 : Carry 1 : Digit carry 2 : Zero flag 3 : Power-down 4 : WDT time-out 5 : Register bank select (For direct addressing) =0 Bank 0 (00h-7Fh) =1 Bank 1 (80h-FFh) 7-6 : Always read as zero. Memory select register Port A data register Port B data register Port C data register Port D data register Port E data register Bit 2-0 - Port E data register. 7-3 - Unimplemented. Always set as 0. Program memory segment register Interrupt control register Bit 0 - PB port change interrupt flag bit. 1 - PB0/IRQ external interrupt flag bit. 2 - Timer0 overflow interrupt flag bit. 3 - PB port change interrupt enable bit. 4 - PB0/IRQ external interrupt enable bit. 5 - Timer0 overflow interrupt enable bit. 6 - Peripheral interrupt enable bit. 7 - Global interrupt enable bit. Peripheral interrupt flag register 1. Bit 0 - Timer1 overflow interrupt flag bit 7-1 - Unimplemented. Always read as 0. Peripheral interrupt flag register 2. Bit 6-0 - Unimplemented. Read as zero. 7 - PD port change interrupt flag bit Timer1 data register low byte. 2005/10 Ver. 1.6
04 05 06 07 08 09
0A 0B
0C
0D
0E
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6
MDT10P65
Unimplemented.. Timer1 control register Bit 0 - Timer1 enable bit 1 - Timer1 clock source select 2 - Timer 1 external clock synchronization control bit 3 - Timer 1 oscillator enable control bit 5-4 - Timer 1 prescaler select bits 7-6 - Unimplemented. Always read as 0. 11-14 Unimplemented. 15 Timer1 compare register 16 Unimplemented. 17 Timer1 compare control register Bit 7-1 -Unimplemented. Always set as 0. 0 - compare enable bit 18-1F Unimplemented. 20-7F General purpose register 80 Same as register 00. 81 TMR register Bit 2-0 - Prescaler rate select bits 3 - Prescaler assign bit 4 - Timer 0 edge select bit 5 - Timer 0 clock source select bit 6 - PB0/IRQ interrupt edge select bit 7 - Port B pull-up enable bit. 82-84 Same as 02H-04H. 85 Port A data direction register. 86 Port B data direction register. 87 Port C data direction register. 88 Port D data direction register. 89 Port E data direction register. Bit 2-0 - Port E data direction register. 7-3 - Unimplemented. Always set as 0. 8A -8B Same as 0AH-0BH. 8C Peripheral interrupt control register 1. Bit 0 - Timer1 overflow interrupt enable bit. 7-1 - Unimplemented. Always set these bits to 0. 8D Peripheral interrupt control register 2 Bit 6-0 - Unimplemented. 7 - PD port change interrupt enable bit.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7
0F 10
2005/10
Ver. 1.6
MDT10P65
8E Power control register. Bit 0 -Unimplemented. Always read as 0. 1 - Power-on reset status bit. 7-2 - Unimplemented. Always read as 0. 8F Unimplemented. 90 PPHE register . ( " 0 " Enable ; " 1 " Disable ) Bit 0-3 - Unimplemented. 4 - PA port pull-up enable bit. 5 - PC port pull-up enable bit. 6 - PD port pull-up enable bit. 7 - PE port pull-up enable bit. 91-9F Unimplemented. A0-FF General purpose register.
7. Timer1 CCP Mode
CCP1CTL Enable
CCP1L
Input COMPARATOR
1 / 2 Output PA7
TMR1L
Clear TMR1L PA7
TRISA< 7 > Output Enable
Input
Output Default
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8
2005/10
Ver. 1.6
MDT10P65
8. Reset Condition for all Registers
Power-On Reset, Power range /MCLR or WDT Reset Wake-up from SLEEP detector Reset 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---- 0000 0000 0001 ---- ---x 1--- ---xxxx xxxx --00 0000 Xxxx xxxx ---- ---0 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 ---- ---0 0--- ------- --#1111 ---x unknown 0000 0000 uuuu uuuu 0000 0000 000# #uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---- 0000 0000 0001 ---- ---u 1--- ---Uuuu uuuu --00 0000 uuuu uuuu ---- ---0 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 ---- ---0 0--- ------- --u1111 ---unimplemented uuuu uuuu uuuu uuuu 0000 0100 000# #uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---- uuuu uuuu uuuu ---- ---u u--- ---Uuuu uuuu --uu uuuu --uu uuuu ---- ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---- ---u u--- ------- --uuuuu ---read as "0"
Register IAR RTCC PCL STATUS MSR PORT A PORT B PORT C PORT D PORT E PCH INTS PIFB1 PIFB2 TMR1L T1STA CCP1L CCP1CTL TMR CPIO A CPIO B CPIO C CPIO D CPIO E PIEB1 PIEB2 PSTA PPHE Note u
Address 00h(80h) 01h 02h(82h) 03h(83h) 04h(84h) 05h 06h 07h 08h 09h 0Ah(8Ah) 0Bh(8Bh) 0Ch 0Dh 0Eh 10h 15h 17h 81h 85h 86h 87h 88h 89h 8Ch 8Dh 8Eh 90h
unchanged
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9
2005/10
Ver. 1.6
MDT10P65
# value depends on the condition of the following table Status bit 4 1 u 1 0 0 1 Status bit 3 1 u 0 1 0 0 PSTA bit 1 0 u u u u u
Condition POWR ON RESET /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Interrupt Wake-up during SLEEP
9. Electrical Characteristics
(Operating temperature at 25 ).
Sym
Description
Condition
Min 2.3
Typ
Max 5.5
Unit V
Vdd Operating voltage VIL Input Low Voltage PA, PB, PC, PD, PE /RES VIH Input high Voltage PA, PB, PC, PD, PE /RES IIL Input leakage current Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V
-0.6 -0.6
1.0 1.0
V V
2.0 3.0
Vdd+0.6 Vdd+0.6 +/-1
V V
A
V V V
VOL Output Low Voltage PA0-PA3 PA4-PA7, PB, PC, PD, PE Vdd=5V, IOL=16mA Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA VOH Output High Voltage PA, PB, PC, PD, PE Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA RHi Pull-up resistance PA0-PA4, PA6-PA7 PB PA5, PC, PD, PE Vdd=5V Vdd=5V Vdd=5V 45K 25K 100K Ohm Ohm Ohm 3.5 4.5 V V 4 0.5 0.2
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10
2005/10
Ver. 1.6
MDT10P65
10. Instruction Set
Instruction Code Mnemonic Operands Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Control I/O port register Store W to register Load register Operation None 0 WT 0 WT, stop OSC W TMODE W W CPIO R r TF, PF TF, PF None None None Z None None Z None C, HC, Z Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000011 TMODE 010000 00000rrr CPIO R 010001 1rrrrrrr STWR R 011000 trrrrrrr LDR R, t
Rt IW [R(0~3) R(4~7)] t R+1 R+1 t t
111010 iiiiiiii LDWI I Load immediate to W 010111 trrrrrrr SWAPR R, t Swap halves register 011001 trrrrrrr INCR R, t Increment register 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero 011011 trrrrrrr ADDWR R, t Add W and register 011100 trrrrrrr SUBWR R, t Subtract W from register 011101 trrrrrrr DECR R, t 011110 trrrrrrr DECRSZ R, t 010010 trrrrrrr ANDWR R, t 110100 iiiiiiii ANDWI i Decrement register Decrement register, skip if zero AND W and register AND W and immediate
W+R t
C, HC, Z R Wt (R+/W+1 t) R R R i R i R 1 1 W W W W W t t t W t W t Z None Z Z Z Z Z Z Z C
010011 trrrrrrr IORWR R, t Inclu. OR W and register 110101 iiiiiiii IORWI i Inclu. OR W and immediate 010100 trrrrrrr XORWR R, t Exclu. OR W and register
110110 iiiiiiii XORWI i Exclu. OR W and immediate i WW 011111 trrrrrrr COMR R, t Complement register /R t 010110 trrrrrrr RRR R, t Rotate right register R(n) R(n-1), C R(7), R(0) C 010101 trrrrrrr RLR R, t Rotate left register R(n) r(n+1), C R(0), R(7) C 010000 1xxxxxxx CLRW Clear working register 0W
C
Z
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11
2005/10
Ver. 1.6
MDT10P65
Instruction Code Mnemonic Operands Function Operation 0 0 1 R R(b) R(b) Status Z None None None None None None None C,HC,Z C,HC,Z None None
010001 0rrrrrrr CLRR R Clear register 0000bb brrrrrrr BCR R, b Bit clear 0010bb brrrrrrr BSR R, b Bit set 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear 0011bb brrrrrrr BTSS R, b Bit Test, skip if set 100nnn nnnnnnnn LCALL n Long CALL subroutine 101nnn nnnnnnnn LJUMP 110001 iiiiiiii RTWI i 110111 iiiiiiii ADDWI 111000 iiiiiiii SUBWI
010000 00001001 RTFI 010000 00000100 RET
Skip if R(b)=0 Skip if R(b)=1 n PC, PC+1 Stack n PC Stack PC, iW PC+1 PC, W+i W i-W W Stack PC, 1 GIS Stack PC
n
Long JUMP to address Return, place immediate to W Add immediate to W Subtract W from immediate Return from interrupt Return from subroutine
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND
: : : : : : : : : : :
Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` ' Exclusive ` ' Logic AND ` '
b t 0 1 R C HC Z / x i n
: : : : : : : : : : : :
Bit position Target Working register General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12
2005/10
Ver. 1.6

▲Up To Search▲

Price & Availability of MDT10P65

	To Download MDT10P65 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .